Processor IP

Micro Architecture

Pipeline

VPU

ICache

DCache

Debug System

Interrupts

Level 2 memory system

System Component

1. Processor IP

2. Micro Architecture

“M” for Integer Multiplication and Division
“A” for Atomic Instructions
“C” for Compressed Instructions
“F” for Single-Precision Floating-Point
“D” for Double-Precision Floating-Point
“B” for Bit Manipulation
“V” for Vector Operations

3. Pipeline

4. Vector Processing Unit

5. ICache

6. DCache

7. Debug System

8. Interrupts

9. Level 2 memory system

10. Bus & System

wrong format(0x...)

wrong format(0x...)

1-core
WH
rv32 IMACFD
M / U / S Mode
CELL
FPU
Customized System
ICache 4-way 32K
DCache 2-way 32K
PTW SV32
IntNode
MasterNode
SlaveNode
Sync
Sync
Sync
Sync
System Bus
Interrupts Bus
Memory Bus
Periphery Bus
Debug
PLIC
256
CLINT
Boot ROM
MEM
MMO
DMA
JTAG
Ext Interrupt
Timer
Micro-Architecture and Subsystem Diagram




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